library verilog;
use verilog.vl_types.all;
entity fpmultiplier_behav is
    port(
        product         : out    vl_logic_vector(31 downto 0);
        ready           : out    vl_logic;
        a               : in     vl_logic_vector(31 downto 0);
        clock           : in     vl_logic;
        nreset          : in     vl_logic
    );
end fpmultiplier_behav;
